diff -Naur prex-0.9.0/bsp/boot/arm/at91/debug.c prex-0.9.0_sasamy/bsp/boot/arm/at91/debug.c
--- prex-0.9.0/bsp/boot/arm/at91/debug.c	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/boot/arm/at91/debug.c	2010-01-21 03:27:03.000000000 +0000
@@ -0,0 +1,66 @@
+/*-
+ * Copyright (c) 2008-2009, Kohsuke Ohtani
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <boot.h>
+
+#define UART_BASE	CONFIG_UART_BASE
+
+/* UART Registers */
+#define UART_CSR	(*(volatile uint32_t *)(UART_BASE + 0x14))
+#define UART_THR	(*(volatile uint32_t *)(UART_BASE + 0x1c))
+
+/* Status Register */
+#define CSR_TXRDY	(0x1 << 1)
+
+/*
+ * Print one chracter
+ */
+void
+debug_putc(int c)
+{
+
+#if defined(DEBUG) && defined(CONFIG_DIAG_SERIAL)
+	while ((UART_CSR & CSR_TXRDY) == 0)
+		;
+	UART_THR = c;
+#endif
+}
+
+/*
+ * Initialize debug port.
+ */
+void
+debug_init(void)
+{
+
+#if defined(DEBUG) && defined(CONFIG_DIAG_SERIAL)
+
+#endif
+}
diff -Naur prex-0.9.0/bsp/boot/arm/at91/Makefile.inc prex-0.9.0_sasamy/bsp/boot/arm/at91/Makefile.inc
--- prex-0.9.0/bsp/boot/arm/at91/Makefile.inc	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/boot/arm/at91/Makefile.inc	2010-01-21 03:27:03.000000000 +0000
@@ -0,0 +1,5 @@
+
+SRCS:=		arm/arch/head.S \
+		arm/at91/startup.c \
+		arm/at91/debug.c
+
diff -Naur prex-0.9.0/bsp/boot/arm/at91/startup.c prex-0.9.0_sasamy/bsp/boot/arm/at91/startup.c
--- prex-0.9.0/bsp/boot/arm/at91/startup.c	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/boot/arm/at91/startup.c	2010-01-21 03:27:03.000000000 +0000
@@ -0,0 +1,63 @@
+/*-
+ * Copyright (c) 2008-2009, Kohsuke Ohtani
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/bootinfo.h>
+#include <boot.h>
+
+/*
+ * Setup boot information.
+ */
+static void
+bootinfo_init(void)
+{
+	struct bootinfo *bi = bootinfo;
+
+	/*
+	 * Screen size
+	 */
+	bi->video.text_x = 80;
+	bi->video.text_y = 25;
+
+	/*
+	 * SDRAM 32M on EBI Chip Select 1
+	 */
+	bi->ram[0].base = CONFIG_RAM_BASE;
+	bi->ram[0].size = CONFIG_RAM_SIZE;
+	bi->ram[0].type = MT_USABLE;
+
+	bi->nr_rams = 1;
+}
+
+void
+startup(void)
+{
+
+	bootinfo_init();
+}
diff -Naur prex-0.9.0/bsp/drv/arm/at91/at91_gpio.c prex-0.9.0_sasamy/bsp/drv/arm/at91/at91_gpio.c
--- prex-0.9.0/bsp/drv/arm/at91/at91_gpio.c	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/drv/arm/at91/at91_gpio.c	2010-01-27 18:37:22.000000000 +0000
@@ -0,0 +1,256 @@
+/*-
+ * Copyright (c) 2006, Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <driver.h>
+#include <busio.h>
+#include "at91_gpio.h"
+
+static int at91_gpio_init(struct driver *);
+
+struct driver at91_gpio_driver = {
+        /* name */      "at91_gpio",
+        /* devops */    NULL,
+        /* devsz */     0,
+        /* flags */     0,
+        /* probe */     NULL,
+        /* init */      at91_gpio_init,
+        /* shutdown */  NULL,
+};
+
+static int at91_gpio_init(struct driver *self)
+{
+
+    return 0;
+}
+
+/* Write PIO register */
+static __inline void write_pio(unsigned int offset, const unsigned int value)
+{
+
+    bus_write_32(BASE_PIOA + offset, value);
+}
+
+/* Read PIO registers */
+static __inline unsigned int read_pio(volatile unsigned int offset)
+{
+
+    return bus_read_32(BASE_PIOA + offset);
+}
+
+/* Convert Pin Number into PIO controller index */
+static __inline unsigned pin_to_controller(unsigned pin)
+{
+
+    return  (pin) / PIO_NB_IO;
+}
+
+/* Convert Pin Number into I/O line index */
+static __inline unsigned pin_to_mask(unsigned pin)
+{
+
+    return 1 << ((pin) % PIO_NB_IO);
+}
+
+/* Mux the pin to the "A" internal peripheral role */
+int
+pio_set_A_periph(unsigned pin, int use_pullup)
+{
+    unsigned pio = pin_to_controller(pin);
+    unsigned mask = pin_to_mask(pin);
+
+    if (pio >= NR_PIO)
+        return -EINVAL;
+
+    write_pio(PIO_IDR(pio), mask);
+    write_pio(use_pullup ? PIO_PPUER(pio) : PIO_PPUDR(pio), mask);
+    write_pio(PIO_ASR(pio), mask);
+    write_pio(PIO_PDR(pio), mask);
+    return 0;
+}
+
+/* Mux the pin to the "B" internal peripheral role */
+int
+pio_set_B_periph(unsigned pin, int use_pullup)
+{
+    unsigned pio = pin_to_controller(pin);
+    unsigned mask = pin_to_mask(pin);
+
+    if (pio >= NR_PIO)
+        return -EINVAL;
+
+    write_pio(PIO_IDR(pio), mask);
+    write_pio((use_pullup ? PIO_PPUER(pio) : PIO_PPUDR(pio)), mask);
+    write_pio(PIO_BSR(pio), mask);
+    write_pio(PIO_PDR(pio), mask);
+    return 0;
+}
+
+/* Mux the pin to the gpio controller input */
+int
+pio_set_gpio_input(unsigned pin, int use_pullup)
+{
+    unsigned pio = pin_to_controller(pin);
+    unsigned mask = pin_to_mask(pin);
+
+    if (pio >= NR_PIO)
+        return -EINVAL;
+
+    write_pio(PIO_IDR(pio), mask);
+    write_pio((use_pullup ? PIO_PPUER(pio) : PIO_PPUDR(pio)), mask);
+    write_pio(PIO_ODR(pio), mask);
+    write_pio(PIO_PER(pio), mask);
+    return 0;
+}
+
+/* Mux the pin to the gpio controller output */
+int
+pio_set_gpio_output(unsigned pin, int value)
+{
+    unsigned pio = pin_to_controller(pin);
+    unsigned mask = pin_to_mask(pin);
+
+    if (pio >= NR_PIO)
+        return -EINVAL;
+
+    write_pio(PIO_IDR(pio), mask);
+    write_pio(PIO_PPUDR(pio), mask);
+    write_pio((value ? PIO_SODR(pio) : PIO_CODR(pio)), mask);
+    write_pio(PIO_OER(pio), mask);
+    write_pio(PIO_PER(pio), mask);
+    return 0;
+}
+
+/*
+ * Enable/disable the glitch filter.
+ * Mostly used with IRQ handling.
+ */
+int
+pio_set_deglitch(unsigned pin, int is_on)
+{
+    unsigned pio = pin_to_controller(pin);
+    unsigned mask = pin_to_mask(pin);
+
+    if (pio >= NR_PIO)
+        return -EINVAL;
+    write_pio((is_on ? PIO_IFER(pio) : PIO_IFDR(pio)), mask);
+    return 0;
+}
+
+/*
+ * Enable/disable the multi-driver. This is only valid for output and
+ * allows the output pin to run as an open collector output.
+ */
+int
+pio_set_multi_drive(unsigned pin, int is_on)
+{
+    unsigned pio = pin_to_controller(pin);
+    unsigned mask = pin_to_mask(pin);
+
+    if (pio >= NR_PIO)
+        return -EINVAL;
+    write_pio((is_on ? PIO_MDER(pio) : PIO_MDDR(pio)), mask);
+    return 0;
+}
+
+/*
+ * Assuming the pin is muxed as a gpio output, set its value.
+ */
+int
+pio_set_gpio_value(unsigned pin, int value)
+{
+    unsigned pio = pin_to_controller(pin);
+    unsigned mask = pin_to_mask(pin);
+
+    if (pio >= NR_PIO)
+        return -EINVAL;
+    write_pio((value ? PIO_SODR(pio) : PIO_CODR(pio)), mask);
+    return 0;
+}
+
+/*
+ * Read the pin's value (works even if it's not muxed as a gpio).
+ */
+int
+pio_get_gpio_value(unsigned pin)
+{
+    unsigned pio = pin_to_controller(pin);
+    unsigned mask = pin_to_mask(pin);
+    uint32_t pdsr;
+
+    if (pio >= NR_PIO)
+        return -EINVAL;
+    pdsr = read_pio(PIO_PDSR(pio));
+    return ((pdsr & mask) ? 1 : 0);
+}
+
+/*
+ * Configure PIO in periph mode according to the platform informations
+ */
+int
+pio_setup (const struct pio_desc *pio_desc)
+{
+    unsigned pio, pin = 0;
+
+    if(!pio_desc) {
+        return 0;
+    }
+
+    /*
+     * Sets all the pio muxing of the corresponding device as defined
+     * in its platform_data struct
+     */
+    while (pio_desc->pin_name) {
+        pio = pin_to_controller(pio_desc->pin_num);
+        if (pio >= NR_PIO)
+            return 0;
+    switch (pio_desc->type) {
+            case PIO_PERIPH_A:
+                 pio_set_A_periph(pio_desc->pin_num,
+                                (pio_desc->attribute & PIO_PULLUP) ? 1 : 0);
+                 break;
+            case PIO_PERIPH_B:
+                 pio_set_B_periph(pio_desc->pin_num,
+                                (pio_desc->attribute & PIO_PULLUP) ? 1 : 0);
+                 break;
+            case PIO_INPUT:
+                 pio_set_deglitch(pio_desc->pin_num,
+                                (pio_desc->attribute & PIO_DEGLITCH)? 1 : 0);
+                 pio_set_gpio_input(pio_desc->pin_num,
+                                (pio_desc->attribute & PIO_PULLUP) ? 1 : 0);
+                 break;
+            case PIO_OUTPUT:
+                 pio_set_multi_drive(pio_desc->pin_num,
+                                (pio_desc->attribute & PIO_OPENDRAIN) ? 1 : 0);
+                 pio_set_gpio_output(pio_desc->pin_num, pio_desc->dft_value);
+                 break;
+            default:
+                 return 0;
+        }
+        ++pin;
+        ++pio_desc;
+    }
+    return pin;
+}
+
diff -Naur prex-0.9.0/bsp/drv/arm/at91/at91_gpio.h prex-0.9.0_sasamy/bsp/drv/arm/at91/at91_gpio.h
--- prex-0.9.0/bsp/drv/arm/at91/at91_gpio.h	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/drv/arm/at91/at91_gpio.h	2010-01-26 06:10:22.000000000 +0000
@@ -0,0 +1,107 @@
+/*-
+ * Copyright (c) 2006, Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _AT91_GPIO_H
+#define _AT91_GPIO_H
+
+#define NR_PIO             (32 * 3)
+#define BASE_PIOA          (0xFFFFF400) /* PIOA Base Address */
+
+/* Register offset in AT91S_PIO structure */
+#define PIO_PER(p)         ( 0 + (p) * 0x200) /* PIO Enable Register */
+#define PIO_PDR(p)         ( 4 + (p) * 0x200) /* PIO Disable Register */
+#define PIO_PSR(p)         ( 8 + (p) * 0x200) /* PIO Status Register */
+#define PIO_OER(p)         (16 + (p) * 0x200) /* Output Enable Register */
+#define PIO_ODR(p)         (20 + (p) * 0x200) /* Output Disable Registerr */
+#define PIO_OSR(p)         (24 + (p) * 0x200) /* Output Status Register */
+#define PIO_IFER(p)        (32 + (p) * 0x200) /* Input Filter Enable Register */
+#define PIO_IFDR(p)        (36 + (p) * 0x200) /* Input Filter Disable Register */
+#define PIO_IFSR(p)        (40 + (p) * 0x200) /* Input Filter Status Register */
+#define PIO_SODR(p)        (48 + (p) * 0x200) /* Set Output Data Register */
+#define PIO_CODR(p)        (52 + (p) * 0x200) /* Clear Output Data Register */
+#define PIO_ODSR(p)        (56 + (p) * 0x200) /* Output Data Status Register */
+#define PIO_PDSR(p)        (60 + (p) * 0x200) /* Pin Data Status Register */
+#define PIO_IER(p)         (64 + (p) * 0x200) /* Interrupt Enable Register */
+#define PIO_IDR(p)         (68 + (p) * 0x200) /* Interrupt Disable Register */
+#define PIO_IMR(p)         (72 + (p) * 0x200) /* Interrupt Mask Register */
+#define PIO_ISR(p)         (76 + (p) * 0x200) /* Interrupt Status Register */
+#define PIO_MDER(p)        (80 + (p) * 0x200) /* Multi-driver Enable Register */
+#define PIO_MDDR(p)        (84 + (p) * 0x200) /* Multi-driver Disable Register */
+#define PIO_MDSR(p)        (88 + (p) * 0x200) /* Multi-driver Status Register */
+#define PIO_PPUDR(p)       (96 + (p) * 0x200) /* Pull-up Disable Register */
+#define PIO_PPUER(p)       (100 + (p) * 0x200) /* Pull-up Enable Register */
+#define PIO_PPUSR(p)       (104 + (p) * 0x200) /* Pull-up Status Register */
+#define PIO_ASR(p)         (112 + (p) * 0x200) /* Select A Register */
+#define PIO_BSR(p)         (116 + (p) * 0x200) /* Select B Register */
+#define PIO_ABSR(p)        (120 + (p) * 0x200) /* AB Select Status Register */
+#define PIO_OWER(p)        (160 + (p) * 0x200) /* Output Write Enable Register */
+#define PIO_OWDR(p)        (164 + (p) * 0x200) /* Output Write Disable Register */
+#define PIO_OWSR(p)        (168 + (p) * 0x200) /* Output Write Status Register */
+
+/* I/O type */
+enum  pio_type {
+    PIO_PERIPH_A,
+    PIO_PERIPH_B,
+    PIO_INPUT,
+    PIO_OUTPUT
+};
+
+/* I/O attributes */
+#define PIO_DEFAULT   (0 << 0)
+#define PIO_PULLUP    (1 << 0)
+#define PIO_DEGLITCH  (1 << 1)
+#define PIO_OPENDRAIN (1 << 2)
+
+struct pio_desc {
+    const char *pin_name;   /* Pin Name */
+    unsigned int pin_num;   /* Pin number */
+    unsigned int dft_value; /* Default value for outputs */
+    unsigned char attribute;
+    enum pio_type type;
+};
+
+/*
+ * pio_device_pio_setup:
+ * Configure PIO in periph mode according to the platform informations
+ */
+extern int pio_set_A_periph(unsigned, int);
+extern int pio_set_B_periph(unsigned, int);
+extern int pio_set_gpio_input(unsigned , int );
+extern int pio_set_gpio_output(unsigned , int );
+extern int pio_set_deglitch(unsigned, int);
+extern int pio_set_multi_drive(unsigned, int);
+extern int pio_set_gpio_value(unsigned ,int );
+extern int pio_get_gpio_value(unsigned);
+extern int pio_setup(const struct pio_desc *);
+
+/* these pin numbers double as IRQ numbers, like AT91C_ID_* values */
+#define PIO_NB_IO   32 /* Number of IO handled by one PIO controller */
+#define PIN_PA(io)  (0 * PIO_NB_IO + io)
+#define PIN_PB(io)  (1 * PIO_NB_IO + io)
+#define PIN_PC(io)  (2 * PIO_NB_IO + io)
+#define PIN_PD(io)  (3 * PIO_NB_IO + io)
+
+#endif /* !_AT91_GPIO_H */
+
diff -Naur prex-0.9.0/bsp/drv/arm/at91/at91_w1.c prex-0.9.0_sasamy/bsp/drv/arm/at91/at91_w1.c
--- prex-0.9.0/bsp/drv/arm/at91/at91_w1.c	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/drv/arm/at91/at91_w1.c	2010-01-28 20:36:24.000000000 +0000
@@ -0,0 +1,207 @@
+/*-
+ * Copyright (c) 2005-2010, Alexander Kudjashev
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * 1-wire DS18S20 digital thermometer
+ */
+
+#include <driver.h>
+#include <busio.h>
+#include "at91_gpio.h"
+
+#define PMC_PCER  (0xFFFFFC10)          /* Peripheral Clock Enable Register */
+#define ID_PIOA   (2)                   /* Parallel IO Controller A */
+#define WPIN      PIN_PC(14)            /* 1-wire data pin */
+#define ID        (ID_PIOA + WPIN / 32) /* Parallel IO Controller ID */
+
+static int at91_w1_init(struct driver *);
+static int at91_w1_read(device_t, char *, size_t *, int);
+
+static struct devops at91_w1_devops = {
+        /* open */      no_open,
+        /* close */     no_close,
+        /* read */      at91_w1_read,
+        /* write */     no_write,
+        /* ioctl */     no_ioctl,
+        /* devctl */    no_devctl,
+};
+
+struct driver at91_w1_driver = {
+        /* name */      "at91_w1",
+        /* devops */    &at91_w1_devops,
+        /* devsz */     0,
+        /* flags */     0,
+        /* probe */     NULL,
+        /* init */      at91_w1_init,
+        /* shutdown */  NULL,
+};
+
+static int
+at91_w1_init(struct driver *self)
+{
+
+    device_create(self, "w1", D_CHR);
+    bus_write_32(PMC_PCER, 1 << ID);
+    pio_set_gpio_output(WPIN, 1);
+    return 0;
+}
+
+static int
+w1_reset(void)
+{
+    int present;
+
+    pio_set_gpio_output(WPIN, 1);
+    delay_usec(10);
+    pio_set_gpio_output(WPIN, 0);
+    delay_usec(500);
+    pio_set_gpio_input(WPIN, 1);
+    delay_usec(40);
+    present = pio_get_gpio_value(WPIN);
+    delay_usec(100);
+    pio_set_gpio_output(WPIN, 1);
+    return !present;
+}
+
+static void
+w1_bit_tx(uint8_t bit)
+{
+
+    pio_set_gpio_output(WPIN, 0);
+    if (bit)
+        delay_usec(6);
+    else
+        delay_usec(60);
+    pio_set_gpio_input(WPIN, 1);
+    if (bit)
+        delay_usec(64);
+    else
+        delay_usec(10);
+}
+
+static int
+w1_bit_rx(void)
+{
+    unsigned int bit;
+
+    pio_set_gpio_output(WPIN, 0);
+    delay_usec(6);
+    pio_set_gpio_input(WPIN, 1);
+    delay_usec(9);
+    bit = pio_get_gpio_value(WPIN);
+    delay_usec(60);
+    return bit ? 1 : 0;
+}
+
+static void
+w1_byte_tx(uint8_t data)
+{
+    int i;
+
+    for (i = 0; i < 8; ++i)
+        w1_bit_tx((data >> i) & 0x01);
+}
+
+unsigned char
+w1_byte_rx(void)
+{
+    int i;
+    uint8_t res = 0;
+
+    for (i = 0; i < 8; ++i)
+        res |= (w1_bit_rx() << i);
+
+    return res;
+}
+
+static void
+crc8(uint8_t b, uint8_t *crc)
+{
+    uint8_t i;
+
+    for (i = 0; i < 8; b = b >> 1, i++)
+        if ((b ^ *crc) & 0x01)
+            *crc = ((*crc ^ 0x18) >> 1) | 0x80;
+        else
+            *crc = (*crc >> 1) & ~0x80;
+}
+
+static int
+at91_w1_read(device_t dev, char *buf, size_t *nbyte, int blkno)
+{
+    int t;
+    uint8_t i, rom[9], rom_crc = 0;
+
+    if (w1_reset()) {
+        w1_byte_tx(0xCC); /* Master issues Skip ROM command */
+        w1_byte_tx(0x44); /* Master issues Convert T command */
+        delay_usec(750000);
+
+        if (w1_reset()) {
+            w1_byte_tx(0xCC); /* Master issues Skip ROM command */
+            w1_byte_tx(0xBE); /* Master issues Read Scratchpad command */
+            /*
+             * Read Scratchpad command response :
+             * byte 0 Temperature LSB
+             * byte 1 Temperature MSB
+             * byte 2 TH Register or User Byte 1* TH Register or User Byte 1
+             * byte 3 TL Register or User Byte 2* TL Register or User Byte 2
+             * byte 4 Reserved
+             * byte 5 Reserved
+             * byte 6 COUNT REMAIN
+             * byte 7 COUNT PER .C
+             * byte 8 CRC
+             */
+            for (i = 0; i < 9; i++) {
+                rom[i] = w1_byte_rx();
+                crc8(rom[i], &rom_crc);
+            }
+            if (!rom_crc) {
+                t = (rom[1] << 8) + rom[0];
+                /* High Resolution Temperature Measurement
+                t = (temp >> 1) - 0.25 + (rom[7] - rom[6])/(float)rom[7]; */
+                if (t & 0x8000) {
+                    t = ~t + 1;
+                    buf[0] = '-';
+                } else
+                    buf[0] = ' ';
+                buf[1] = (t >> 1) / 10;
+                buf[1] = buf[1] ? buf[1] + '0' : ' ';
+                buf[2] = '0' + (t >> 1) % 10;
+                buf[3] = '.';
+                buf[4] = (t & 0x01) ? '0' + 5 : '0';
+                buf[5] = '\n';
+                buf[6] = 0;
+
+                *nbyte = 7;
+            }
+        }
+    }
+    return 0;
+}
diff -Naur prex-0.9.0/bsp/drv/arm/at91/Makefile.inc prex-0.9.0_sasamy/bsp/drv/arm/at91/Makefile.inc
--- prex-0.9.0/bsp/drv/arm/at91/Makefile.inc	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/drv/arm/at91/Makefile.inc	2010-01-26 15:21:20.000000000 +0000
@@ -0,0 +1,3 @@
+
+SRCS-$(CONFIG_AT91_GPIO)+=		arm/at91/at91_gpio.c
+SRCS-$(CONFIG_AT91_W1)+=		arm/at91/at91_w1.c
diff -Naur prex-0.9.0/bsp/drv/dev/rtc/at91_rtc.c prex-0.9.0_sasamy/bsp/drv/dev/rtc/at91_rtc.c
--- prex-0.9.0/bsp/drv/dev/rtc/at91_rtc.c	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/drv/dev/rtc/at91_rtc.c	2010-01-21 03:27:03.000000000 +0000
@@ -0,0 +1,89 @@
+/*-
+ * Copyright (c) 2005-2009, Kohsuke Ohtani
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * at91_rtc.c - Atmel at91 RTT 
+ */
+
+#include <sys/time.h>
+#include <sys/ioctl.h>
+
+#include <driver.h>
+#include <rtc.h>
+
+#define RTC_BASE	0xfffffd20
+
+#define RTC_MR		(RTC_BASE + 0x00)
+#define RTC_AR		(RTC_BASE + 0x04)
+#define RTC_VR		(RTC_BASE + 0x08)
+#define RTC_SR		(RTC_BASE + 0x0c)
+
+static int	at91_rtc_init(struct driver *);
+static int	at91_rtc_gettime(void *, struct timeval *);
+static int	at91_rtc_settime(void *, struct timeval *);
+
+
+struct driver at91_rtc_driver = {
+	/* name */	"at91_rtc",
+	/* devops */	NULL,
+	/* devsz */	0,
+	/* flags */	0,
+	/* probe */	NULL,
+	/* init */	at91_rtc_init,
+	/* shutdown */	NULL,
+};
+
+struct rtc_ops at91_rtc_ops = {
+	/* gettime */	at91_rtc_gettime,
+	/* settime */	at91_rtc_settime,
+};
+
+static int
+at91_rtc_gettime(void *aux, struct timeval *tv)
+{
+
+	tv->tv_usec = 0;
+	tv->tv_sec = bus_read_32(RTC_VR);
+	printf("******* sec=%d\n", tv->tv_sec);
+	return 0;
+}
+
+static int
+at91_rtc_settime(void *aux, struct timeval *ts)
+{
+	return 0;
+}
+
+static int
+at91_rtc_init(struct driver *self)
+{
+
+	rtc_attach(&at91_rtc_ops, NULL);
+	return 0;
+}
diff -Naur prex-0.9.0/bsp/drv/dev/rtc/Makefile.inc prex-0.9.0_sasamy/bsp/drv/dev/rtc/Makefile.inc
--- prex-0.9.0/bsp/drv/dev/rtc/Makefile.inc	2009-10-01 12:33:27.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/drv/dev/rtc/Makefile.inc	2010-01-21 03:27:03.000000000 +0000
@@ -2,3 +2,4 @@
 SRCS-$(CONFIG_RTC)+=		dev/rtc/rtc.c
 SRCS-$(CONFIG_MC146818)+=	dev/rtc/mc146818.c
 SRCS-$(CONFIG_PL030)+=		dev/rtc/pl030.c
+SRCS-$(CONFIG_AT91_RTC)+=	dev/rtc/at91_rtc.c
diff -Naur prex-0.9.0/bsp/drv/dev/serial/at91_uart.c prex-0.9.0_sasamy/bsp/drv/dev/serial/at91_uart.c
--- prex-0.9.0/bsp/drv/dev/serial/at91_uart.c	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/drv/dev/serial/at91_uart.c	2010-01-29 05:00:24.000000000 +0000
@@ -0,0 +1,184 @@
+/*-
+ * Copyright (c) 2008-2009, Kohsuke Ohtani
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * at91_uart.c - Atmel at91 UART
+ */
+
+#include <driver.h>
+#include <tty.h>
+#include <serial.h>
+
+/* #define DEBUG_AT91_UART 1 */
+
+#ifdef DEBUG_AT91_UART
+#define DPRINTF(a) printf a
+#else
+#define DPRINTF(a)
+#endif
+
+#define UART_BASE   CONFIG_UART_BASE
+#define UART_IRQ    CONFIG_UART_IRQ
+/* UART Registers */
+#define UART_CR     (UART_BASE + 0x00)
+#define UART_MR     (UART_BASE + 0x04)
+#define UART_IER    (UART_BASE + 0x08)
+#define UART_IDR    (UART_BASE + 0x0c)
+#define UART_IMR    (UART_BASE + 0x10)
+#define UART_CSR    (UART_BASE + 0x14)
+#define UART_RHR    (UART_BASE + 0x18)
+#define UART_THR    (UART_BASE + 0x1c)
+#define UART_BRGR   (UART_BASE + 0x20)
+
+/* Control Register */
+#define CR_RSTRX    (0x1 << 2)
+#define CR_RSTTX    (0x1 << 3)
+#define CR_RXEN     (0x1 << 4)
+#define CR_RXDIS    (0x1 << 5)
+#define CR_TXEN     (0x1 << 6)
+#define CR_TXDIS    (0x1 << 7)
+#define CR_RSTSTA   (0x1 << 8)
+
+/* Mode Register */
+#define MR_PAR      (0x7 << 9)
+
+/* UART flags */
+#define IR_RXRDY    (1 << 0)        /* Receiver Ready */
+#define IR_TXRDY    (1 << 1)        /* Transmitter Ready */
+
+/* Forward functions */
+static int  at91_uart_init(struct driver *);
+static void at91_uart_xmt_char(struct serial_port *, char);
+static char at91_uart_rcv_char(struct serial_port *);
+static void at91_uart_set_poll(struct serial_port *, int);
+static void at91_uart_start(struct serial_port *);
+static void at91_uart_stop(struct serial_port *);
+
+
+struct driver at91_uart_driver = {
+    /* name */  "at91_uart",
+    /* devops */    NULL,
+    /* devsz */ 0,
+    /* flags */ 0,
+    /* probe */ NULL,
+    /* init */  at91_uart_init,
+    /* detach */    NULL,
+};
+
+static struct serial_ops at91_uart_ops = {
+    /* xmt_char */  at91_uart_xmt_char,
+    /* rcv_char */  at91_uart_rcv_char,
+    /* set_poll */  at91_uart_set_poll,
+    /* start */ at91_uart_start,
+    /* stop */  at91_uart_stop,
+};
+
+static struct serial_port at91_uart_port;
+
+
+static void
+at91_uart_xmt_char(struct serial_port *sp, char c)
+{
+
+    while ((bus_read_32(UART_CSR) & IR_TXRDY) == 0)
+        ;
+    bus_write_32(UART_THR, (uint32_t)c);
+}
+
+static char
+at91_uart_rcv_char(struct serial_port *sp)
+{
+    char c;
+
+    while ((bus_read_32(UART_CSR) & IR_RXRDY) == 0)
+        ;
+    c = bus_read_32(UART_RHR) & 0xff;
+    return c;
+}
+
+static void
+at91_uart_set_poll(struct serial_port *sp, int on)
+{
+
+    if (on) {
+        /* Disable interrupt for polling mode */
+        bus_write_32(UART_IDR, IR_RXRDY);
+    } else
+        bus_write_32(UART_IER, IR_RXRDY);
+}
+
+static int
+at91_uart_isr(void *arg)
+{
+    struct serial_port *sp = arg;
+    int c;
+    uint32_t status;
+
+    status = bus_read_32(UART_CSR);
+
+    if (status & IR_RXRDY) {    /* Receive interrupt */
+        c = bus_read_32(UART_RHR);
+        serial_rcv_char(sp, c);
+    }
+    if (status & IR_TXRDY) {    /*  Transmit interrupt */
+        serial_xmt_done(sp);
+    }
+    return 0;
+}
+
+static void
+at91_uart_start(struct serial_port *sp)
+{
+
+    /* Disable all interrupt */
+    bus_write_32(UART_IDR, 0xffffffff);
+    bus_read_32(UART_CSR);
+
+    /* Install interrupt handler */
+    sp->irq = irq_attach(UART_IRQ, IPL_COMM, 1, at91_uart_isr, IST_NONE, sp);
+
+    /* Enable TX/RX interrupt */
+    bus_write_32(UART_IER, IR_RXRDY);
+}
+
+static void
+at91_uart_stop(struct serial_port *sp)
+{
+
+    bus_write_32(UART_IDR, 0xffffffff); /* Disable all interrupts */
+    bus_write_32(UART_CR, (CR_RXDIS | CR_TXDIS));
+}
+
+static int
+at91_uart_init(struct driver *self)
+{
+
+    serial_attach(&at91_uart_ops, &at91_uart_port);
+    return 0;
+}
diff -Naur prex-0.9.0/bsp/drv/dev/serial/Makefile.inc prex-0.9.0_sasamy/bsp/drv/dev/serial/Makefile.inc
--- prex-0.9.0/bsp/drv/dev/serial/Makefile.inc	2009-10-01 12:33:28.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/drv/dev/serial/Makefile.inc	2010-01-21 03:27:03.000000000 +0000
@@ -2,3 +2,4 @@
 SRCS-$(CONFIG_SERIAL)+=		dev/serial/serial.c
 SRCS-$(CONFIG_NS16550)+=	dev/serial/ns16550.c
 SRCS-$(CONFIG_PL011)+=		dev/serial/pl011.c
+SRCS-$(CONFIG_AT91_UART)+=	dev/serial/at91_uart.c
diff -Naur prex-0.9.0/bsp/hal/arm/arch/locore.S prex-0.9.0_sasamy/bsp/hal/arm/arch/locore.S
--- prex-0.9.0/bsp/hal/arm/arch/locore.S	2009-07-29 09:52:52.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/hal/arm/arch/locore.S	2010-01-21 04:13:25.000000000 +0000
@@ -88,6 +88,8 @@
 init_done:	 	.word	init_done_value
 #ifdef CONFIG_MMU
 reload_pc_target:	.word	reload_pc
+clear_ctl:              .word   0x00007f3f
+set_ctl:                .word   0x0000313d
 #endif
 
 ENTRY(reset_entry)
@@ -118,57 +120,71 @@
 
 #ifdef CONFIG_MMU
 	/*
-	 * Setup control register
-	 */
-	mov	r0, #CTL_DEFAULT
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
 	 * Initialize page table
 	 * The physical address 0-4M is mapped on virtual address 2G.
 	 */
-	mov	r1, #BOOT_PGD_PHYS		/* Clear page directory */
-	mov	r2, #(BOOT_PGD_PHYS + 0x4000)	/* +16k */
+        ldr     r1, =BOOT_PGD_PHYS              /* Clear page directory */
+        add     r2, r1, #0x4000                 /* +16k */
 	mov	r0, #0
 1:
 	str	r0, [r1], #4
 	teq	r1, r2
 	bne	1b
 
-	mov	r1, #(BOOT_PGD_PHYS + 0x2000) /* Set PTE0 address in pgd */
-	mov	r0, #BOOT_PTE0_PHYS	/* WBUF/CACHE/SYSTEM attribute */
-	orr	r0, r0, #0x03
+        ldr     r1, =(BOOT_PGD_PHYS + 0x2000 + PHYS >> 18) /* Set PTE0 address in pgd */
+        ldr     r0, =(BOOT_PTE0_PHYS | 0x11)
 	str	r0, [r1]
 
-	mov	r1, #BOOT_PTE0_PHYS	/* Fill boot page table entry */
-	add	r2, r1, #0x1000
-	mov	r0, #0x1e
+	ldr	r1, =BOOT_PTE0_PHYS	/* Fill boot page table entry */
+	add	r2, r1, #0x400
+	ldr	r0, =(PHYS | 0x552)
 1:
 	str	r0, [r1], #4
 	add	r0, r0, #0x1000
 	teq	r1, r2
 	bne	1b
 
+        ldr     r1, =(BOOT_PGD_PHYS + 0x3ffc)   /* Set PTE1 address */
+        ldr     r0, =(BOOT_PTE1_PHYS | 0x11)
+        str     r0, [r1]
+
+        ldr     r1, =BOOT_PTE1_PHYS             /*  Clear PTE1 page table */
+        add     r2, r1, #0x1000
+        mov     r0, #0
+1:
+        str     r0, [r1], #4
+        teq     r1, r2
+        bne     1b
+        
+        ldr     r1, = BOOT_PTE1_PHYS
+        ldr     r0, =(CONFIG_UART_BASE | 0x552)                 /* premap diag port */
+        str     r0, [r1, #(CONFIG_UART_BASE >> 10 & 0x3fc)]
+        
+        ldr     r0, =0x552                                      /* premap vector page */
+        str     r0, [r1, #(CONFIG_ARM_VECTORS >> 10 & 0x3fc)]
+
 	/*
 	 * Enable paging
-	 * The physical address 0-4M is temporarily mapped to virtial
-	 * address 0-4M. This is needed to enable paging.
 	 */
-	mov	r1, #BOOT_PGD_PHYS	/* Set PTE0 address in pgd */
-	mov	r0, #BOOT_PTE0_PHYS	/* WBUF/CACHE/SYSTEM attribute */
-	orr	r0, r0, #0x03
+        ldr     r1, =(BOOT_PGD_PHYS + PHYS >> 18)    /* Set PTE0 address in pgd */
+        ldr     r0, =(BOOT_PTE0_PHYS | 0x11)
 	str	r0, [r1]
 
+        mov     r0, #4                  /* disable write-back */
+        mcr     p15, 7, r0, c15, c0, 0 
+
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
 	mcr	p15, 0, r0, c8, c7, 0	/* flush I,D TLBs */
-	mov	r1, #BOOT_PGD_PHYS
+	ldr	r1, =BOOT_PGD_PHYS
 	mcr	p15, 0, r1, c2, c0, 0	/* load page table pointer */
 	mov	r0, #-1
 	mcr	p15, 0, r0, c3, c0	/* load domain access register */
 	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, r0, #0x1000		/* I-cache enable */
-	orr	r0, r0, #0x003d		/* Write buffer, mmu */
+        ldr     r1, clear_ctl
+        bic     r0, r0, r1
+        ldr     r1, set_ctl
+        orr     r0, r0, r1
 	mcr	p15, 0, r0, c1, c0, 0
 
 	/*
@@ -177,17 +193,6 @@
 	ldr	pc, reload_pc_target	/* Reset pc here */
 reload_pc:
 
-	/*
-	 * Unmap 0-4M.
-	 * Since the first page must be accessible for exception
-	 * vector, we have to map it later.
-	 */
-	mov	r1, #BOOT_PGD_PHYS	/* Set PTE0 address in pgd */
-	add	r1, r1, #KERNBASE
-	mov	r0, #0
-	str	r0, [r1]
-	mcr	p15, 0, r0, c8, c7, 0	/* flush I,D TLBs */
-
 #endif /* !CONFIG_MMU */
 
 	/*
diff -Naur prex-0.9.0/bsp/hal/arm/arch/mmu.c prex-0.9.0_sasamy/bsp/hal/arm/arch/mmu.c
--- prex-0.9.0/bsp/hal/arm/arch/mmu.c	2009-10-01 12:28:55.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/hal/arm/arch/mmu.c	2010-01-21 03:27:31.000000000 +0000
@@ -143,6 +143,7 @@
 	default:
 		panic("mmu_map");
 	}
+pte_flag = (uint32_t)(PTE_PRESENT | PTE_SYSTEM);
 	/*
 	 * Map all pages
 	 */
@@ -198,8 +199,6 @@
 	i = PAGE_DIR(KERNBASE);
 	memcpy(&pgd[i], &boot_pgd[i], (size_t)(L1TBL_SIZE - i * 4));
 
-	/* Map vector page (address 0) */
-	mmu_map(pgd, 0, 0, PAGE_SIZE, PG_SYSTEM);
 	return pgd;
 }
 
@@ -272,20 +271,6 @@
 }
 
 /*
- * Map I/O memory for diagnostic device at very early stage.
- */
-void
-mmu_premap(paddr_t phys, vaddr_t virt)
-{
-	pte_t pte = (pte_t)BOOT_PTE1;
-
-	memset(pte, 0, L2TBL_SIZE);
-	boot_pgd[PAGE_DIR(virt)] = (uint32_t)kvtop(pte) | PDE_PRESENT;
-	pte[PAGE_TABLE(virt)] = (uint32_t)phys | PTE_PRESENT | PTE_SYSTEM;
-	flush_tlb();
-}
-
-/*
  * Initialize mmu
  *
  * Paging is already enabled in locore.S. And, physical address
@@ -320,6 +305,6 @@
 	/*
 	 * Map vector page.
 	 */
-	if (mmu_map(boot_pgd, 0, CONFIG_ARM_VECTORS, PAGE_SIZE, PG_SYSTEM))
+	if (mmu_map(boot_pgd, PHYS, CONFIG_ARM_VECTORS, PAGE_SIZE, PG_SYSTEM))
 		panic("mmu_init");
 }
diff -Naur prex-0.9.0/bsp/hal/arm/at91/clock.c prex-0.9.0_sasamy/bsp/hal/arm/at91/clock.c
--- prex-0.9.0/bsp/hal/arm/at91/clock.c	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/hal/arm/at91/clock.c	2010-01-29 04:20:35.000000000 +0000
@@ -0,0 +1,144 @@
+/*-
+ * Copyright (c) 2008, Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * clock.c - Atmel at91 TC clock driver
+ */
+
+#include <kernel.h>
+#include <timer.h>
+#include <irq.h>
+#include <cpufunc.h>
+#include <sys/ipl.h>
+
+#include "platform.h"
+
+/* Peripheral Clock Enable Register */
+#define PMC_PCER (*(volatile uint32_t *)(0xfffffc10)) /* Peripheral Clock Enable Register */
+
+/* Peripheral id TC0 */
+#define ID_TC  17
+
+/* Timer Counter registers */
+#define TC_CCR (*(volatile uint32_t *)(TC_BASE + 0x0000)) /* Channel Control Register */
+#define TC_CMR (*(volatile uint32_t *)(TC_BASE + 0x0004)) /* Channel Mode Register */
+#define TC_RC  (*(volatile uint32_t *)(TC_BASE + 0x001c)) /* Register C */
+#define TC_SR  (*(volatile uint32_t *)(TC_BASE + 0x0020)) /* Status Register */
+#define TC_IER (*(volatile uint32_t *)(TC_BASE + 0x0024)) /* Interrupt Enable Register */
+#define TC_IDR (*(volatile uint32_t *)(TC_BASE + 0x0028)) /* Interrupt Disable Register */
+
+#define CCR_CLKEN              (0x1 <<  0) /* Counter Clock Enable Command */
+#define CCR_CLKDIS             (0x1 <<  1) /* Counter Clock Disable Command */
+#define CCR_SWTRG              (0x1 <<  2) /* Software Trigger Command */
+#define CMR_WAVE               (0x1 << 15)
+#define CMR_WAVESEL_UP_AUTO    (0x2 << 13) /* UP mode with automatic trigger on RC Compare */
+#define SR_CPCS                (0x1 <<  4) /* RC Compare */
+
+/*
+ * Finds the best MCK divisor given the timer frequency and MCK
+ */
+unsigned char
+find_divisor(unsigned int freq,
+             unsigned int *div,
+             unsigned int *tcclks)
+{
+    const unsigned int divisors[5] = {2, 8, 32, 128, CONFIG_MCK / 32768};
+    unsigned int index = 0;
+
+    /* Satisfy lower bound */
+    while (freq < ((CONFIG_MCK / divisors[index]) / 65536)) {
+        index++;
+        /* If no divisor can be found, return 0 */
+        if (index == 5)
+            return 0;
+    }
+
+    /* Try to maximise DIV while satisfying upper bound */
+    while (index < 4) {
+        if (freq > (CONFIG_MCK / divisors[index + 1]))
+            break;
+        index++;
+    }
+
+    /* Store results */
+    if (div)
+        *div = divisors[index];
+    if (tcclks)
+        *tcclks = index;
+    return 1;
+}
+
+/*
+ * Clock interrupt service routine.
+ * No H/W reprogram is required.
+ */
+static int
+clock_isr(void *arg)
+{
+    volatile uint32_t piv;
+
+    /* Acknowledging the interrupt */
+    piv = TC_SR;
+    splhigh();
+    timer_handler();
+    spl0();
+    return INT_DONE;
+}
+
+/*
+ * Initialize clock H/W chip.
+ * Setup clock tick rate and install clock ISR.
+ */
+void
+clock_init(void)
+{
+    irq_t clock_irq;
+    unsigned int div, tcclks, sr;
+
+    /* Enable TC */
+    PMC_PCER = 1 << ID_TC;
+
+    find_divisor(CONFIG_HZ, &div, &tcclks);
+    /* Disable TC clock */
+    TC_CCR = CCR_CLKDIS;
+    /* Disable interrupts */
+    TC_IDR = 0xffffffff;
+    /* Clear status register */
+    sr = TC_SR;
+    /* Set mode */
+    TC_CMR = tcclks | CMR_WAVE | CMR_WAVESEL_UP_AUTO;
+    TC_RC = CONFIG_MCK / (CONFIG_HZ * div);
+
+    clock_irq = irq_attach(ID_TC, IPL_CLOCK, 1, &clock_isr, IST_NONE, NULL);
+
+    /* Enable timer interrupt */
+    TC_IER = SR_CPCS;
+    /* Start timer */
+    TC_CCR = CCR_CLKEN | CCR_SWTRG;
+
+    DPRINTF(("Clock rate: %d ticks/sec\n", CONFIG_HZ));
+}
+
+
diff -Naur prex-0.9.0/bsp/hal/arm/at91/diag.c prex-0.9.0_sasamy/bsp/hal/arm/at91/diag.c
--- prex-0.9.0/bsp/hal/arm/at91/diag.c	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/hal/arm/at91/diag.c	2010-01-21 03:27:31.000000000 +0000
@@ -0,0 +1,71 @@
+/*-
+ * Copyright (c) 2008, Kohsuke Ohtani
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * diag.c - diagnostic message support
+ */
+
+#include <sys/bootinfo.h>
+#include <kernel.h>
+#include <cpufunc.h>
+
+#include "platform.h"
+
+/* UART Registers */
+#define UART_CSR	(*(volatile uint32_t *)(UART_BASE + 0x14))
+#define UART_THR	(*(volatile uint32_t *)(UART_BASE + 0x1c))
+
+/* Status Register */
+#define CSR_TXRDY	(0x1 << 1)
+
+static void
+serial_putc(char c)
+{
+
+	while ((UART_CSR & CSR_TXRDY) == 0)
+		;
+	UART_THR = (uint32_t)c;
+}
+
+void
+diag_puts(char *buf)
+{
+
+	while (*buf) {
+		if (*buf == '\n')
+			serial_putc('\r');
+		serial_putc(*buf++);
+	}
+}
+
+void
+diag_init(void)
+{
+
+}
diff -Naur prex-0.9.0/bsp/hal/arm/at91/interrupt.c prex-0.9.0_sasamy/bsp/hal/arm/at91/interrupt.c
--- prex-0.9.0/bsp/hal/arm/at91/interrupt.c	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/hal/arm/at91/interrupt.c	2010-01-29 01:52:49.000000000 +0000
@@ -0,0 +1,219 @@
+/*-
+ * Copyright (c) 2008, Kohsuke Ohtani
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * interrupt.c - interrupt handling routines
+ */
+
+#include <sys/ipl.h>
+#include <kernel.h>
+#include <hal.h>
+#include <irq.h>
+#include <cpufunc.h>
+#include <context.h>
+#include <locore.h>
+
+#include "platform.h"
+
+/* Registers for Advanced Interrupt Controller */
+#define AIC_SMR		((volatile uint32_t *)(AIC_BASE + 0x00))
+#define AIC_SVR		((volatile uint32_t *)(AIC_BASE + 0x80))
+
+#define	AIC_IVR		(*(volatile uint32_t *)(AIC_BASE + 0x100))
+#define	AIC_IECR	(*(volatile uint32_t *)(AIC_BASE + 0x120))
+#define	AIC_IDCR	(*(volatile uint32_t *)(AIC_BASE + 0x124))
+#define	AIC_ICCR	(*(volatile uint32_t *)(AIC_BASE + 0x128))
+#define AIC_EOICR	(*(volatile uint32_t *)(AIC_BASE + 0x130))
+#define AIC_SPU		(*(volatile uint32_t *)(AIC_BASE + 0x134))
+#define AIC_DCR		(*(volatile uint32_t *)(AIC_BASE + 0x138))
+
+/* Source Mode Register */
+#define	SMR_PRIOR		(7 << 0)
+#define	SMR_SRCTYPE		(3 << 5)
+#define	SMR_SRCTYPE_LOW		(0 << 5)
+#define	SMR_SRCTYPE_FALLING	(1 << 5)
+#define	SMR_SRCTYPE_HIGH	(2 << 5)
+#define	SMR_SRCTYPE_RISING	(3 << 5)
+
+/*
+ * Interrupt Priority Level
+ *
+ * Each interrupt has its logical priority level, with 0 being
+ * the lowest priority. While some ISR is running, all lower
+ * priority interrupts are masked off.
+ */
+volatile int irq_level;
+
+/*
+ * Table to map Prex interrupt priority to
+ * interrupt controller H/W priority
+ */
+static const uint32_t ipl_to_prio[NIPLS] = {
+	0,		/* IPL_NONE */
+	0,		/* IPL_COMM */
+	0,		/* IPL_BLOCK */
+	1,		/* IPL_NET */
+	1,		/* IPL_DISPLAY */
+	2,		/* IPL_INPUT */
+	2,		/* IPL_AUDIO */
+	3,		/* IPL_BUS */
+	4,		/* IPL_RTC */
+	5,		/* IPL_PROFILE */
+	6,		/* IPL_CLOCK */
+	7		/* IPL_HIGH */
+};
+
+/*
+ * Table to save IPL value for each interrupt vector
+ */
+static int vector_to_ipl[NIRQS];
+
+/*
+ * Enable interrupt on AIC.
+ * Assumes CPU interrupt is disabled in caller.
+ */
+void
+interrupt_unmask(int vector, int level)
+{
+
+	uint32_t prio;
+
+	/* Save IPL for future use */
+	vector_to_ipl[vector] = level;
+
+	/* Get priority level */
+	prio = ipl_to_prio[level];
+
+	/* Config irq line priority */
+	AIC_SMR[vector] = (prio & SMR_PRIOR);
+
+	/* Enable irq line */
+	AIC_IECR = (1 << vector);
+}
+
+/*
+ * Disable interrupt on AIC.
+ * Interrupt must be disabled when this routine is called.
+ */
+void
+interrupt_mask(int vector)
+{
+
+	AIC_IDCR = (1 << vector);
+}
+
+/*
+ * Setup interrupt mode.
+ * Select whether an interrupt trigger is edge or level.
+ */
+void
+interrupt_setup(int vector, int mode)
+{
+	uint32_t srctype;
+	
+	switch (mode) {
+		case IMODE_LEVEL:
+			srctype = SMR_SRCTYPE_HIGH;
+			break;
+		case IMODE_EDGE:
+			srctype = SMR_SRCTYPE_RISING;
+			break;
+		default:
+			srctype = SMR_SRCTYPE_HIGH;
+	}
+
+	AIC_SMR[vector] &= ~SMR_SRCTYPE;
+	AIC_SMR[vector] |= srctype;
+}
+
+/*
+ * Common interrupt handler.
+ */
+void
+interrupt_handler(void)
+{
+	int vector, old_ipl;
+
+	/* Get interrupt source */
+	vector = AIC_IVR;
+
+	/* Detects a spurious interrupt */
+	if (vector == NIRQS)
+		goto out;
+
+	/* Adjust interrupt level */
+	old_ipl = irq_level;
+	irq_level = vector_to_ipl[vector];
+
+	/* Allow another interrupt that has higher priority */
+	splon();
+
+	/* Dispatch interrupt */
+	irq_handler(vector);
+
+	sploff();
+
+	/* Restore interrupt level */
+	irq_level = old_ipl;
+	
+out:
+	/* Restore the previous current level if one exists on the stack */
+	AIC_EOICR = 0;
+}
+
+/*
+ * Initialize the AIC interrupt controller.
+ * All interrupts will be masked off.
+ */
+void
+interrupt_init(void)
+{
+	unsigned int i;
+
+	irq_level = IPL_NONE;
+	
+	for (i = 0; i < NIRQS; i++) {
+		/* Put irq number in Source Vector Register */
+		AIC_SVR[i] = i;
+
+		/* Unstack nested interrupts */
+		if (i < 8)
+			AIC_EOICR = 0;
+	}
+
+	/* Spurious Interrupt ID in Spurious Vector Register is NIRQS */
+	AIC_SPU = NIRQS;
+
+	/* No debugging in AIC */
+	AIC_DCR = 0;
+
+	/* Disable and clear all interrupts initially */
+	AIC_IDCR = 0xffffffff;
+	AIC_ICCR = 0xffffffff;
+}
diff -Naur prex-0.9.0/bsp/hal/arm/at91/machdep.c prex-0.9.0_sasamy/bsp/hal/arm/at91/machdep.c
--- prex-0.9.0/bsp/hal/arm/at91/machdep.c	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/hal/arm/at91/machdep.c	2010-01-21 03:27:31.000000000 +0000
@@ -0,0 +1,161 @@
+/*-
+ * Copyright (c) 2008-2009, Kohsuke Ohtani
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * machdep.c - machine-dependent routines for at91
+ */
+
+#include <machine/syspage.h>
+#include <sys/power.h>
+#include <sys/bootinfo.h>
+#include <kernel.h>
+#include <page.h>
+#include <mmu.h>
+#include <cpu.h>
+#include <cpufunc.h>
+#include <locore.h>
+
+#include "platform.h"
+
+#ifdef CONFIG_MMU
+/*
+ * Virtual and physical address mapping
+ *
+ *      { virtual, physical, size, type }
+ */
+struct mmumap mmumap_table[] =
+{
+	/*
+	 * External SDRAM (32M)
+	 */
+	{ 0xa0000000, CONFIG_RAM_BASE, CONFIG_RAM_SIZE, VMT_RAM },
+
+	/*
+	 * Internal Peripherals (544K)
+	 */
+	{ 0xfffa0000, 0xfffa0000, 0x44000, VMT_IO }, 
+
+        { 0xffffc000, 0xffffc000, 0x4000, VMT_IO },
+
+	{ 0,0,0,0 }
+};
+#endif
+
+/*
+ * Idle
+ */
+void
+machine_idle(void)
+{
+
+	cpu_idle();
+}
+
+/*
+ * Reset system.
+ */
+static void
+machine_reset(void)
+{
+
+	for (;;) ;
+	/* NOTREACHED */
+}
+
+/*
+ * Set system power
+ */
+void
+machine_powerdown(int state)
+{
+
+	splhigh();
+
+	DPRINTF(("Power down machine\n"));
+
+	switch (state) {
+	case PWR_OFF:
+		for (;;)
+			cpu_idle();
+		/* NOTREACHED */
+		break;
+	case PWR_REBOOT:
+		machine_reset();
+		/* NOTREACHED */
+		break;
+	}
+}
+
+/*
+ * Return pointer to the boot information.
+ */
+void
+machine_bootinfo(struct bootinfo **bip)
+{
+
+	*bip = (struct bootinfo *)BOOTINFO;
+}
+
+void
+machine_abort(void)
+{
+
+	for (;;)
+		cpu_idle();
+}
+
+/*
+ * Machine-dependent startup code
+ */
+void
+machine_startup(void)
+{
+	/*
+	 * Initialize CPU and basic hardware.
+	 */
+	cpu_init();
+	cache_init();
+
+	/*
+	 * Reserve system pages.
+	 */
+	page_reserve(kvtop(SYSPAGE), SYSPAGESZ);
+
+	/*
+	 * Setup vector page.
+	 */
+	vector_copy(SYSPAGE);
+
+#ifdef CONFIG_MMU
+	/*
+	 * Initialize MMU
+	 */
+	mmu_init(mmumap_table);
+#endif
+}
diff -Naur prex-0.9.0/bsp/hal/arm/at91/Makefile.inc prex-0.9.0_sasamy/bsp/hal/arm/at91/Makefile.inc
--- prex-0.9.0/bsp/hal/arm/at91/Makefile.inc	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/hal/arm/at91/Makefile.inc	2010-01-21 03:27:03.000000000 +0000
@@ -0,0 +1,16 @@
+
+SRCS:=		arm/arch/locore.S \
+		arm/arch/cpufunc.S \
+		arm/arch/cpu.c \
+		arm/arch/trap.c \
+		arm/arch/context.c \
+		arm/at91/interrupt.c \
+		arm/at91/clock.c \
+		arm/at91/machdep.c
+
+ifeq ($(CONFIG_MMU),y)
+SRCS+=		arm/arch/mmu.c
+endif
+ifeq ($(DEBUG),1)
+SRCS+=		arm/at91/diag.c
+endif
diff -Naur prex-0.9.0/bsp/hal/arm/at91/platform.h prex-0.9.0_sasamy/bsp/hal/arm/at91/platform.h
--- prex-0.9.0/bsp/hal/arm/at91/platform.h	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/hal/arm/at91/platform.h	2010-01-29 04:13:44.000000000 +0000
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2008, Kohsuke Ohtani
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _AT91_PLATFORM_H
+#define _AT91_PLATFORM_H
+
+/* number of interrupt vectors */
+#define NIRQS	32
+
+#define UART_BASE	0xfffff200
+/* System Peripherals */
+#define AIC_BASE	0xfffff000
+#define TC_BASE		0xfffa0000
+
+#endif /* !_AT91_PLATFORM_H */
diff -Naur prex-0.9.0/bsp/hal/arm/include/mmu.h prex-0.9.0_sasamy/bsp/hal/arm/include/mmu.h
--- prex-0.9.0/bsp/hal/arm/include/mmu.h	2009-10-01 12:28:53.000000000 +0000
+++ prex-0.9.0_sasamy/bsp/hal/arm/include/mmu.h	2010-01-21 03:27:31.000000000 +0000
@@ -36,13 +36,13 @@
 typedef uint32_t	*pte_t;		/* page table entry */
 
 #define L1TBL_SIZE	0x4000
-#define L2TBL_SIZE	0x1000
+#define L2TBL_SIZE	0x400
 
 /*
  * Page directory entry (L1)
  */
-#define PDE_PRESENT	0x00000003
-#define PDE_ADDRESS	0xfffff000
+#define PDE_PRESENT	0x00000011
+#define PDE_ADDRESS	0xfffffc00
 
 /*
  * Page table entry (L2)
@@ -50,11 +50,11 @@
 #define PTE_PRESENT	0x00000002
 #define PTE_WBUF	0x00000004
 #define PTE_CACHE	0x00000008
-#define PTE_SYSTEM	0x00000010
-#define PTE_USER_RO	0x00000020
-#define PTE_USER_RW	0x00000030
-#define PTE_ATTR_MASK	0x00000030
-#define PTE_ADDRESS	0xfffffc00
+#define PTE_SYSTEM	0x00000550
+#define PTE_USER_RO	0x00000aa0
+#define PTE_USER_RW	0x00000ff0
+#define PTE_ATTR_MASK	0x00000ff0
+#define PTE_ADDRESS	0xfffff000
 
 /*
  *  Virtual and physical address translation
diff -Naur prex-0.9.0/conf/arm/at91 prex-0.9.0_sasamy/conf/arm/at91
--- prex-0.9.0/conf/arm/at91	1970-01-01 00:00:00.000000000 +0000
+++ prex-0.9.0_sasamy/conf/arm/at91	2010-01-29 05:08:26.000000000 +0000
@@ -0,0 +1,134 @@
+#
+# Prex system configuration file
+#
+
+#
+# Make options
+#
+makeoptions     GCCFLAGS+= -mcpu=arm9tdmi
+
+#
+# Memory address
+#
+memory		RAM_BASE	0x20000000	# Start of ram
+memory		RAM_SIZE	0x2000000	# Size  of ram
+memory		LOADER_TEXT	0x20010000	# Start of boot loader
+memory		KERNEL_TEXT	0xa0080000	# Start of kernel
+memory		BOOTIMG_BASE	0xa0012000	# Location of boot image
+memory		SYSPAGE_BASE	0xa0000000	# Location of system page
+
+#
+# Tunable paramters
+#
+options 	HZ=1000		# Ticks/second of the clock
+options 	TIME_SLICE=50	# Context switch ratio (msec)
+options 	OPEN_MAX=16	# Max open files per process
+options 	BUF_CACHE=32	# Blocks for buffer cache
+options 	FS_THREADS=4	# Number of file system threads
+
+#
+# Platform settings
+#
+options	        ARM926EJS	# Processor core
+options         MMU		# Memory management unit
+options         CACHE		# Cache memory
+#options        FPU		# Floating point unit
+#options        ROMBOOT		# Boot from ROM
+options         BOOTDISK	# Disk for /boot directory
+
+#
+# General setup
+#
+options 	POSIX		# POSIX support
+options 	CMDBOX		# Core utilities
+options 	TINY		# Optimize for size
+
+#
+# Kernel hacking
+#
+#options 	KD		# Kernel debugger
+#options 	AUDIT		# Security auditing
+
+#
+# Diagnostic options
+#
+options 	DIAG_SERIAL	# Diagnostic via serial port
+
+#
+# File systems
+#
+options 	FIFOFS		# FIFO & Pipe
+options 	DEVFS		# Device file system
+options 	RAMFS		# RAM file system
+options 	ARFS		# Archive file system
+#options 	FATFS		# FAT file system
+
+#
+# Power management
+#
+#options 	PM		# Power management
+#options 	PM_POWERSAVE	# Power policy: Battery optimized
+#options 	PM_PERFORMANCE	# Power policy: Parformance optimized
+
+#
+# Device drivers (initialization order)
+#
+#device		pm		# Power management
+device		cons		# System console
+device		serial		# Generic serial
+device  	at91_uart	# AT91 UART
+device		rtc		# Logical RTC
+device 		at91_rtc	# AT91 RTT
+device		null		# NULL device
+device		zero		# Zero device
+device		ramdisk		# RAM disk
+device		at91_gpio	# AT91 GPIO
+device		at91_w1		# AT91 GPIO
+
+#
+# Hardware configuations
+#
+options		ARM_VECTORS=0xffff0000
+options		MCK=98304000
+options		UART_BASE=0xfffff200
+options		UART_IRQ=1
+
+#
+# Command box
+#
+command 	cat
+command 	clear
+command 	cp
+command 	date
+command 	dmesg
+command 	echo
+command 	free
+command 	head
+command 	hostname
+command 	kill
+command 	ls
+command 	mkdir
+command 	more
+command 	mv
+command 	nice
+command 	printenv
+command 	ps
+command 	pwd
+command 	rm
+command 	rmdir
+command 	sh
+command 	sleep
+command 	sync
+#command 	test
+command 	touch
+command 	uname
+
+#
+# Adminisrative tools
+#
+#command 	diskutil
+#command 	install
+#command 	pmctrl
+#command 	ktrace
+#command 	lock
+#command 	debug
diff -Naur prex-0.9.0/conf/etc/files.mk prex-0.9.0_sasamy/conf/etc/files.mk
--- prex-0.9.0/conf/etc/files.mk	2009-10-01 12:14:25.000000000 +0000
+++ prex-0.9.0_sasamy/conf/etc/files.mk	2010-01-21 03:27:31.000000000 +0000
@@ -63,6 +63,6 @@
 #FILES+= 	$(SRCDIR)/usr/test/stderr/stderr
 #FILES+= 	$(SRCDIR)/usr/test/umount/umount
 
-FILES+=		$(SRCDIR)/doc/LICENSE
+#FILES+=		$(SRCDIR)/doc/LICENSE
 
 endif	# !CONFIG_POSIX
diff -Naur prex-0.9.0/conf/etc/fstab prex-0.9.0_sasamy/conf/etc/fstab
--- prex-0.9.0/conf/etc/fstab	2009-10-01 12:31:55.000000000 +0000
+++ prex-0.9.0_sasamy/conf/etc/fstab	2010-01-21 03:27:31.000000000 +0000
@@ -6,7 +6,7 @@
 /dev/ram0	/boot		arfs
 none		/dev		devfs
 none		/mnt/fifo	fifofs
-/dev/fd0	/mnt/floppy	fatfs
+#/dev/fd0	/mnt/floppy	fatfs
 
 #/dev/mtd0	/bin		ffs
 #/dev/mtd1	/etc		ffs
diff -Naur prex-0.9.0/include/arm/syspage.h prex-0.9.0_sasamy/include/arm/syspage.h
--- prex-0.9.0/include/arm/syspage.h	2009-05-14 12:23:00.000000000 +0000
+++ prex-0.9.0_sasamy/include/arm/syspage.h	2010-01-21 03:27:31.000000000 +0000
@@ -81,9 +81,10 @@
 #define BOOT_PTE0	(SYSPAGE + 0x8000)
 #define BOOT_PTE1	(SYSPAGE + 0x9000)
 
-#define BOOT_PGD_PHYS	0x4000
-#define BOOT_PTE0_PHYS	0x8000
-#define BOOT_PTE1_PHYS	0x9000
+#define PHYS           CONFIG_RAM_BASE
+#define BOOT_PGD_PHYS  (PHYS + 0x4000)
+#define BOOT_PTE0_PHYS (PHYS + 0x8000)
+#define BOOT_PTE1_PHYS (PHYS + 0x9000)
 
 #define INTSTKSZ	0x1000
 #define SYSSTKSZ	0x1000
diff -Naur prex-0.9.0/sys/include/hal.h prex-0.9.0_sasamy/sys/include/hal.h
--- prex-0.9.0/sys/include/hal.h	2009-10-01 12:13:44.000000000 +0000
+++ prex-0.9.0_sasamy/sys/include/hal.h	2010-01-21 03:27:31.000000000 +0000
@@ -104,7 +104,6 @@
 void	  context_dump(context_t);
 
 void	  mmu_init(struct mmumap *);
-void	  mmu_premap(paddr_t, vaddr_t);
 pgd_t	  mmu_newmap(void);
 void	  mmu_terminate(pgd_t);
 int	  mmu_map(pgd_t, paddr_t, vaddr_t, size_t, int);
